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[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] user_logic_Open_I2C

Description: iic implementation,用verilog实现了IIC标准协议的功能-iic implementation, verilog achieved using standard protocols IIC function
Platform: | Size: 12288 | Author: | Hits:

[Crack Hack] des

Description: 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过-Using Verilog language code of the Data Encryption Standard, in the simulation had QUARTUS5.1
Platform: | Size: 1436672 | Author: zhang feng | Hits:

[VHDL-FPGA-Verilog] bbb

Description: AVS运动补偿电路的VLSI设计与实现 提出了一种基于AVS标准的高效的运动补偿电路硬件结构，该设计采用了8 X 8块级流 水线操作，运动矢量归一化处理和插值滤波器组保证了流水线的高效运行以及硬件资源的最优 利用。采用Verilog语言完成了VLSI设计，并通过EDA软件给出仿真和综合结果。-AVS motion compensation circuit of VLSI Design and Implementation of a standard based on the AVS motion compensation circuit efficient hardware structure, the design used 8 X 8 block-level pipelining, the normalized motion vector processing and interpolation filter bank guarantee efficient operation of the pipeline, as well as the optimal use of hardware resources. Using Verilog language completed VLSI design and EDA software through simulation and synthesis results.
Platform: | Size: 216064 | Author: sss | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

[Com Port] iic

Description: iic 总线 verilog 源代码 标准i2c总线， 有sda scl 时钟，频率自定-IIC bus standard Verilog source code i2c bus, has sda scl clock, the frequency of self-
Platform: | Size: 2048 | Author: johnnyz | Hits:

[mpeg mp3] +++ANNEX_AB

Description: mp3编码器1，根据mp3标准编写，串行结构，c语言，具有比较好的可读性。-mp3 encoder 1, in accordance with the standard preparation of mp3, serial structure, c language, has a better readability.
Platform: | Size: 27648 | Author: libaiqsl | Hits:

[Com Port] I2C_verilog

Description: I2C总线是Philips公司推出的双向两线串行通讯标准，具有接口线少、通讯效率高等特点。将I2C总线设计成FPGA内部的模块，可以方便FPGA与其他具有I2C总线的设备通信。-I2C bus is Philips has introduced two-way two-wire serial communication standard, with fewer line interface, communications and high efficiency. I2C bus will be designed within the FPGA module, can easily FPGA and other devices with I2C bus communication.
Platform: | Size: 8192 | Author: 沈天平 | Hits:

[Program doc] G0709

Description: sdh 标准 itu G0709.rar-SDH standard itu G0709.rar
Platform: | Size: 149504 | Author: 陈小冲 | Hits:

[VHDL-FPGA-Verilog] LCD1602

Description: LCD1602显示源代码 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是标准的16×2字符型液晶模块上显示字符串； 3-LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display the string 3
Platform: | Size: 716800 | Author: 张海风 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Platform: | Size: 1474560 | Author: 王刚 | Hits:

[Graph program] rgb2ycrcb

Description: 真正可用的RGB转YCbCr的verilog程序，输出格式为标准BT.656格式，经本人亲自编写并验证，可在硬件上正常工作。-Truly available to the Verilog RGB to YCbCr procedures BT.656 output format as the standard format, as I personally prepared and verified in the hardware work correctly.
Platform: | Size: 2048 | Author: cloud | Hits:

[VHDL-FPGA-Verilog] JPEGvhdl

Description: JPEG标准下图象压缩的vhdl实现工程，文件包括一个图像。-JPEG image compression standard works of VHDL realize that the document includes an image.
Platform: | Size: 260096 | Author: 姚大雷 | Hits:

[VHDL-FPGA-Verilog] fadd

Description: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Platform: | Size: 2048 | Author: 兰兰 | Hits:

[VHDL-FPGA-Verilog] ps2

Description: ps2接口源程序。标准的键盘和鼠标接口，在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
Platform: | Size: 23552 | Author: Alex | Hits:

[Streaming Mpeg4] MPEG4_ASP(chn)

Description: MPEG4_ASP将对MPEG4标准中的Advanced Simple Profile（ASP）做一个完整的说明-MPEG4 will MPEG4_ASP standard Advanced Simple Profile (ASP) to do a complete description of
Platform: | Size: 656384 | Author: haifeng | Hits:

[Graph program] JPEG2000

Description: JPEG 2000 国际标准系列 ISO/IEC FCD15444-1~6-JPEG 2000 international standard series ISO/IEC FCD15444-1 ~ 6
Platform: | Size: 3887104 | Author: 李才伟 | Hits:

[VHDL-FPGA-Verilog] ahbapb

Description: AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
Platform: | Size: 4096 | Author: LIANG | Hits:

[VHDL-FPGA-Verilog] sha-1

Description: 本算法基于leon2协处理器接口标准，内含testbench，在modelsim中仿真通过，在ise9.2中综合及后仿真通过。-The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
Platform: | Size: 15360 | Author: ninghuiming | Hits:

[VHDL-FPGA-Verilog] uart_verilog

Description: 用verilog编写的标准异步串行通行程序，供大家参考！-Prepared using Verilog standard asynchronous serial passage procedures for your reference!
Platform: | Size: 5120 | Author: 谢谢 | Hits:
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